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Full Chip STA Lead
Description:
A "Full Chip STA Lead" is a key role in semiconductor companies, responsible for leading Static Timing Analysis (STA) activities for complex full-chip designs. The job description for this role typically includes the following responsibilities and qualifications: Responsibilities: Timing Closure: Lead and manage the full-chip STA process to achieve timing closure goals, including setup and hold time analysis, clock domain crossing (CDC) analysis, and signal integrity (SI) analysis. STA Methodology: Develop and implement STA methodologies and best practices to ensure accurate and efficient timing analysis of full-chip designs, including setup of timing constraints and constraints validation. Tool Selection and Optimization: Evaluate, select, and optimize STA tools and scripts for timing analysis, including tools like Synopsys PrimeTime, Cadence Tempus, and Mentor Calibre. Timing Constraints: Define, validate, and maintain timing constraints, including clock definitions, input/output delays, false path constraints, and multicycle paths. Timing Analysis: Perform static timing analysis for full-chip designs, analyze timing paths, identify timing violations, and work with design teams to resolve timing issues. Clock Domain Crossing (CDC) Analysis: Perform CDC analysis to identify and mitigate metastability issues, clock domain crossings, and data synchronization problems. Signal Integrity (SI) Analysis: Collaborate with SI engineers to analyze signal integrity issues, including noise, jitter, and crosstalk, and ensure timing closure with SI constraints. Collaboration: Work closely with design teams, physical design teams, verification teams, and other stakeholders to understand design requirements, resolve timing issues, and ensure successful tape-out. Documentation: Maintain documentation related to timing constraints, STA reports, timing closure status, and issues encountered during STA activities. Qualifications: Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Experience: Several years of experience in static timing analysis (STA) for full-chip designs, including experience in a lead or senior role. STA Tools: Proficiency in using industry-standard STA tools such as Synopsys PrimeTime, Cadence Tempus, and Mentor Calibre, including scripting skills in Tcl, Perl, or Python for automation. Timing Closure: Expertise in achieving timing closure for full-chip designs, including understanding of setup and hold time violations, clock tree synthesis (CTS), and optimization techniques. CDC and SI Analysis: Experience in clock domain crossing (CDC) analysis, signal integrity (SI) analysis, and related methodologies to ensure reliable and robust chip performance. Collaboration Skills: Strong communication, teamwork, and collaboration skills to work effectively with cross-functional teams and stakeholders, including design, physical design, and verification teams. Problem-Solving: Excellent analytical and problem-solving skills to identify and resolve timing issues, debug STA failures, and propose effective solutions. Leadership: Leadership skills to lead and mentor junior STA engineers, drive timing closure activities, and manage project timelines and deliverables. Overall, a Full Chip STA Lead plays a critical role in ensuring the timing integrity and reliability of full-chip designs, contributing to the successful tape-out and production of high-quality semiconductor productsPowered by JazzHR
Company:
Zealogics.com
Posted:
March 21 on The Resumator
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More About this Listing: Full Chip STA Lead
Full Chip STA Lead is a Jobs Full Chip Sta Lead Job at Zealogics.com located in India. Find other listings like Full Chip STA Lead by searching Oodle for Jobs Full Chip Sta Lead Jobs.
Full Chip STA Lead is a Jobs Full Chip Sta Lead Job at Zealogics.com located in India. Find other listings like Full Chip STA Lead by searching Oodle for Jobs Full Chip Sta Lead Jobs.