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IP Verification Engineer - System Verilog (5-10 yrs) Bangalore
Location:
Bangalore
Description:
Our leading clients provide end-to-end support for the semiconductor industry.They are looking for IP Verification to be based at Bangalore with the following skills :- Total 5 - 10 years of experience in IP Design Verification- System Verilog or Specman expertise OVM/UVM/eRM expertise highly desired - Must have strong knowledge of protocols- Ability and desire to learn new methodologies, languages, protocols etc- Notice Period: 30 days or serving 60 days or 90 Day notice period- Education: BE/BTech, ME/MTech ( VLSI Domain ) (ref:hirist.tech)
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More About this Listing: IP Verification Engineer - System Verilog (5-10 yrs) Bangalore
IP Verification Engineer - System Verilog (5-10 yrs) Bangalore is a Engineering Engineer Job at MY Search located in India. Find other listings like IP Verification Engineer - System Verilog (5-10 yrs) Bangalore by searching Oodle for Engineering Engineer Jobs.
IP Verification Engineer - System Verilog (5-10 yrs) Bangalore is a Engineering Engineer Job at MY Search located in India. Find other listings like IP Verification Engineer - System Verilog (5-10 yrs) Bangalore by searching Oodle for Engineering Engineer Jobs.