Digicomm
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Pre-Silicon Validation Engineer - System Verilog (3-8 yrs)
Location:
Bangalore/Noida/Hyderabad/Pune
Description:
Job Title : Pre-Silicon Validation EngineerJob Description :Responsibilities :Validation Planning : - Collaborate with design and architecture teams to define validation requirements and develop detailed validation plans for complex semiconductor designs.Testbench Development : - Design and develop scalable and reusable validation testbenches using System Verilog and UVM methodology to verify functionality and performance requirements.Testcase Development : - Create testcases based on architectural specifications, functional requirements, and design intent to cover all aspects of design functionality.Simulation : - Execute validation tests using RTL simulation tools (e.g., Cadence Incisive, Synopsys VCS) to verify design functionality, timing, and power requirements.Emulation : - Utilize emulation platforms (e.g., Cadence Palladium, Mentor Veloce) to perform acceleration and in-circuit emulation (ICE) for faster validation of large-scale designs. (ref:hirist.tech)
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More About this Listing: Pre-Silicon Validation Engineer - System Verilog (3-8 yrs)
Pre-Silicon Validation Engineer - System Verilog (3-8 yrs) is a Engineering Validation Engineer Job at Digicomm located in India. Find other listings like Pre-Silicon Validation Engineer - System Verilog (3-8 yrs) by searching Oodle for Engineering Validation Engineer Jobs.
Pre-Silicon Validation Engineer - System Verilog (3-8 yrs) is a Engineering Validation Engineer Job at Digicomm located in India. Find other listings like Pre-Silicon Validation Engineer - System Verilog (3-8 yrs) by searching Oodle for Engineering Validation Engineer Jobs.