Troy Consultancy
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Verification Engineer - System Verilog/UVM (3-7 yrs) Bangalore/Hyderabad
Location:
Bangalore/Hyderabad
Description:
Job Summary : We are seeking a skilled Verification Engineer with 3-7 years of experience in SV/UVM methodology to join our team. The ideal candidate will be responsible for developing testbenches for non-volatile memory (NVM) IP, creating agents, adapting existing tests, defining verification coverage, and ensuring the quality and effectiveness of the verification process. Proficiency in SV/UVM methodology, Certitude, and documentation of verification results are essential for success in this role.Key Responsibilities :Testbench Development :- Develop SV/UVM testbenches for non-volatile memory IP verification.Agent Creation : - Create agents for driving and monitoring signals in the test environment.Test Adaptation and Creation :- Make adaptations to existing tests and create new tests to verify new features of the NVM IP.Test Validation :- Validate relevant tests to ensure they are passing and accurately verifying the functionality of the NVM IP.Verification Coverage Definition :- Define verification coverage metrics, including both structural and functional coverage.Testbench Qualification :- Qualify testbenches using Certitude or similar tools to ensure their reliability and effectiveness.Documentation :- Document verification results, including test plans, test cases, and test reports.Verification Proof :- Provide proof that relevant tests are passing and effectively verifying the NVM IP.Coverage Proof :- Demonstrate proof that verification coverage goals (structural and functional) are achieved.Quality Assurance :- Ensure that testbenches meet the required quality standards and are capable of thoroughly verifying the NVM IP.Qualifications and Experience :- Bachelor's or Master's degree.- 3 to 7 years of experience in ASIC or FPGA verification, with a focus on SV/UVM methodology.- Experience in developing SV/UVM testbenches for complex IP verification, preferably non-volatile memory.- Proficiency in scripting languages such as Perl or Python for test automation.- Experience with verification tools such as Certitude or similar qualification tools.- Strong understanding of verification methodologies, including coverage-driven verification.- Excellent problem-solving skills and attention to detail.- Good communication skills and the ability to work effectively in a team environment. (ref:hirist.tech)
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More About this Listing: Verification Engineer - System Verilog/UVM (3-7 yrs) Bangalore/Hyderabad
Verification Engineer - System Verilog/UVM (3-7 yrs) Bangalore/Hyderabad is a Engineering Engineer Job at Troy Consultancy located in India. Find other listings like Verification Engineer - System Verilog/UVM (3-7 yrs) Bangalore/Hyderabad by searching Oodle for Engineering Engineer Jobs.
Verification Engineer - System Verilog/UVM (3-7 yrs) Bangalore/Hyderabad is a Engineering Engineer Job at Troy Consultancy located in India. Find other listings like Verification Engineer - System Verilog/UVM (3-7 yrs) Bangalore/Hyderabad by searching Oodle for Engineering Engineer Jobs.