ACZ Global Private Limited
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Mixed Signal ASIC Design Lead - System Verilog (10-20 yrs) Pune
Location:
Pune
Description:
Experience : 10 years + relevant industry experienceRole : Lead of Mixed Signal ASIC DesignJob Description :- Lead and coordinate a team of 5 engineers in mixed-signal, RF, analog and digital domain- Design and guide projects on advanced mixed-signal circuits data converters, sub-sampling phase locked loops, serdes and RF circuits in CMOS and BiCMOS and low-power & low-voltage applications.- Skilled in Cadence custom IC EDA tools. - Knowledge of Keysight Pathway desired. - Achieve successful realization of the layout in close collaboration with layout team.- Work with application developers to co-develop hardware and software systems.- Collaborate with teams in India and abroad during project implementation phase. Requirements :- PhD/Master degrees from top universities- Must have a Proven track record of taking multiple mixed-signal ICs through the entire development cycle, from concept to production.- + 10 years' experience industrial experience in analog and mixed-signal design.- Successful realization of more than 5 ASIC designs- In depth knowledge of Cadence custom IC EDA tools- Proficiency in system and behavioural modeling using MATLAB, System Verilog, Verilog-A/AMS.- Experience with HDL languages Verilog and/or VHDL is desired.- Scripting skills like Python, Perl and C is a plus.- Experience with design, implementation, and development environments for reconfigurable systems (such as FPGAs) is a plus.- Experience with the silicon manufacturers and working with various CMOS process technologies is a plus. (ref:hirist.tech)
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More About this Listing: Mixed Signal ASIC Design Lead - System Verilog (10-20 yrs) Pune
Mixed Signal ASIC Design Lead - System Verilog (10-20 yrs) Pune is a Jobs Mixed Signal Asic Design Lead Job at ACZ Global located in India. Find other listings like Mixed Signal ASIC Design Lead - System Verilog (10-20 yrs) Pune by searching Oodle for Jobs Mixed Signal Asic Design Lead Jobs.
Mixed Signal ASIC Design Lead - System Verilog (10-20 yrs) Pune is a Jobs Mixed Signal Asic Design Lead Job at ACZ Global located in India. Find other listings like Mixed Signal ASIC Design Lead - System Verilog (10-20 yrs) Pune by searching Oodle for Jobs Mixed Signal Asic Design Lead Jobs.