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RTL Design Engineer - System Verilog (5-15 yrs) Bangalore
Location:
Bangalore
Description:
Job Description- Synthesis, Equivalence Checking, Clock-Domain Crossing (CDC) Analysis, Area/Power optimizations, Linting, Static Timing Analysis (STA)- Write design specifications for different functional blocks on a chip, Create micro-architecture diagrams of functional blocks, Design functional blocks using System Verilog RTL code, conduct Synthesis and place and route to meet timing / area goals- Contribute to Design Verification, Synthesis, Power Reduction, Timing Convergence & Floorplan efforts- Responsible for logic implementation of complex design block(s) using RTL coding techniques (Verilog)- Code Verilog RTL for high performance designs with supervision from manager and input from peers and architects in the engineering team- You handle Verilog RTL logic design and debug- Develop RTL for logic blocks and participate in Front End activities like Synthesis, Timing Closure & FPGA implementation- Contribute as a design engineer developing the next-generation of multi-core processors- Specify, design, and synthesize RTL blocks, optimize and floorplan them- Work with verification engineers to ensure their accuracy (ref:hirist.tech)
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More About this Listing: RTL Design Engineer - System Verilog (5-15 yrs) Bangalore
RTL Design Engineer - System Verilog (5-15 yrs) Bangalore is a Engineering Design Engineer Job at Mysearch located in India. Find other listings like RTL Design Engineer - System Verilog (5-15 yrs) Bangalore by searching Oodle for Engineering Design Engineer Jobs.
RTL Design Engineer - System Verilog (5-15 yrs) Bangalore is a Engineering Design Engineer Job at Mysearch located in India. Find other listings like RTL Design Engineer - System Verilog (5-15 yrs) Bangalore by searching Oodle for Engineering Design Engineer Jobs.