People Impact
This listing was posted on hirist.
Senior STA Engineer - ASIC Design (5-10 yrs) Noida/Hyderabad/Bangalore/Pune
Location:
Noida/Hyderabad/Bangalore/Pune
Description:
We are seeking a highly skilled Senior Static Timing Analysis (STA) Engineer with 5-10 years of experience in digital ASIC design and timing closure. As a Senior STA Engineer, you will play a key role in ensuring the timing integrity and performance of our advanced semiconductor designs.Key Responsibilities :- Perform comprehensive static timing analysis (STA) on digital designs to identify timing violations and optimize design performance.- Collaborate closely with design, physical design, and verification teams to resolve timing issues and meet timing closure targets.- Develop and maintain timing constraints for synthesis, place and route, and timing closure.- Utilize industry-standard EDA tools for STA, such as Synopsys Primetime or Cadence Tempus, to analyze setup and hold timing paths.- Conduct timing ECOs (Engineering Change Orders) to address timing violations post-layout.- Work on advanced timing closure techniques including multi-mode, multi-corner (MMMC) analysis, and OCV (On-Chip Variation) analysis.- Drive improvements in design methodologies and flows to enhance timing closure efficiency.- Provide guidance and mentorship to junior STA engineers.Required Skills and Qualifications :- Bachelor's or Master's degree in Electrical Engineering or related field.- 5-10 years of hands-on experience in static timing analysis (STA) for complex ASIC designs.- Proficiency in industry-standard EDA tools for STA (e.g., Synopsys Primetime, Cadence Tempus).- Strong understanding of timing constraints and methodologies for timing closure.- Experience with scripting languages (e.g., Tcl, Perl, Python) for automation of timing analysis tasks.- Solid knowledge of digital design concepts, RTL coding, and synthesis.- Ability to analyze complex timing issues and propose effective solutions.- Excellent communication and collaboration skills.Preferred Qualifications :- Experience with low-power design and clock domain crossing (CDC) analysis.- Familiarity with physical design concepts and methodologies.- Knowledge of statistical timing analysis and timing sign-off methodologies.Location - Noida, Bangalore, Hyderabad, Pune (ref:hirist.tech)
Visit Our Partner Website
This listing was posted on another website. Click here to open: Go to hirist
Important Safety Tips
- Always meet the employer in person.
- Avoid sharing sensitive personal and financial information.
- Avoid employment offers that require a deposit or investment.
To learn more, visit the Safety Center or click here to report this listing.
More About this Listing: Senior STA Engineer - ASIC Design (5-10 yrs) Noida/Hyderabad/Bangalore/Pune
Senior STA Engineer - ASIC Design (5-10 yrs) Noida/Hyderabad/Bangalore/Pune is a Engineering Engineer Job at People Impact located in India. Find other listings like Senior STA Engineer - ASIC Design (5-10 yrs) Noida/Hyderabad/Bangalore/Pune by searching Oodle for Engineering Engineer Jobs.
Senior STA Engineer - ASIC Design (5-10 yrs) Noida/Hyderabad/Bangalore/Pune is a Engineering Engineer Job at People Impact located in India. Find other listings like Senior STA Engineer - ASIC Design (5-10 yrs) Noida/Hyderabad/Bangalore/Pune by searching Oodle for Engineering Engineer Jobs.