SILCOSYS Solutions Pvt. Ltd
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Design Verification Engineer - UVM/System Verilog (3-6 yrs) Bangalore/Pune
Location:
Bangalore/Pune
Description:
Job Description :We are seeking a skilled and dedicated Design Verification Engineer with 3 to 6 years of experience to join our innovative team. The ideal candidate will have a strong background in design verification methodologies and will be responsible for ensuring the quality and reliability of our ASIC and SoC designs.This role requires a comprehensive understanding of verification processes, testbench development, and simulation tools.Key Responsibilities :- Verification Planning : Develop and execute verification plans based on design specifications and requirements.- Testbench Development : Design and implement testbenches using SystemVerilog/UVM to verify complex digital designs.- Functional Coverage : Define and measure functional coverage to ensure comprehensive verification of the design.- Simulation and Debugging : Perform simulations, analyze results, and debug issues to ensure the design meets functional and performance requirements.- Verification IP Integration : Integrate and utilize third-party verification IPs and create reusable verification components.- Collaboration : Work closely with RTL designers, architects, and other verification engineers to resolve issues and improve design quality.- Regression Testing : Set up and maintain regression test environments to ensure continuous - verification and identify issues early in the design cycle.- Documentation : Create and maintain detailed documentation of verification plans, methodologies, test cases, and results.- Process Improvement : Contribute to the development and enhancement of verification methodologies and flows.Required Qualifications :- Education : Bachelor's or Master's degree in Computer Science or a related field.- Experience : 3 to 6 years of hands-on experience in design verification.Technical Skills :- Proficiency in SystemVerilog and UVM methodology.- Experience with simulation tools such as Synopsys VCS, Cadence Incisive/Xcelium, or Mentor Graphics Questa.- Strong understanding of digital design and verification concepts.- Experience with functional coverage and code coverage analysis.- Familiarity with scripting languages (TCL, Perl, Python) for automation of verification tasks.Soft Skills :- Strong analytical and problem-solving abilities.- Excellent communication and teamwork skills.- Ability to work independently and manage multiple tasks effectively.- Detail-oriented with a commitment to quality. (ref:hirist.tech)
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More About this Listing: Design Verification Engineer - UVM/System Verilog (3-6 yrs) Bangalore/Pune
Design Verification Engineer - UVM/System Verilog (3-6 yrs) Bangalore/Pune is a Engineering Engineer Job at Silcosys Solutions located in India. Find other listings like Design Verification Engineer - UVM/System Verilog (3-6 yrs) Bangalore/Pune by searching Oodle for Engineering Engineer Jobs.
Design Verification Engineer - UVM/System Verilog (3-6 yrs) Bangalore/Pune is a Engineering Engineer Job at Silcosys Solutions located in India. Find other listings like Design Verification Engineer - UVM/System Verilog (3-6 yrs) Bangalore/Pune by searching Oodle for Engineering Engineer Jobs.