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RTL Design Engineer - System Verilog (5-15 yrs) Bangalore
Engineering · Mysearch · BangaloreJob Description- Synthesis, Equivalence Checking, Clock-Domain Crossing (CDC) Analysis, Area/Power optimizations, Linting, Static Timing Analysis (STA)- Write design specifications for different functional blocks on a chip, Create micro-architectu...MySearch ·3 weeks ago on hiristTools -
DFT Engineer - MBIST/ATPG (3-15 yrs) Bangalore/Hyderabad
Engineering · Mysearch · Bangalore/HyderabadJob Description :- SCAN stuck-at and at-speed techniques.- Fundamentals of SCAN stuck-at and at-speed techniques. - Expertise in handling Mentor Graphics EDT logic. - Knowledge on On chip clock controller (OCC).- Pattern generation with Mentor Gra...MySearch ·3 weeks ago on hiristTools