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RTL Design Engineer - System Verilog (5-15 yrs) Bangalore
Engineering · Mysearch · BangaloreJob Description- Synthesis, Equivalence Checking, Clock-Domain Crossing (CDC) Analysis, Area/Power optimizations, Linting, Static Timing Analysis (STA)- Write design specifications for different functional blocks on a chip, Create micro-architectu...MySearch ·2 weeks ago on hiristTools -
Analog Cricuit Design Engineer - CMOS (5-10 yrs) Hyderabad/Bangalore
Engineering · Mysearch · Hyderabad/BangaloreJob Description :- 5 to 8-year experience in analog circuit design in advanced deep sub-micron CMOS process.- Expertise in Cadence ADE, Synopsys Primetime/Finesim is a must. Exposure to netlist driven simulation flow is an added advamntage.- Knowl...MySearch ·4 weeks ago on hiristTools