Spruce IT Pvt. Ltd.
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Design Verification Lead - System Verilog (10-12 yrs) Anywhere in India/Multiple
Location:
Anywhere in India/Multiple Locations
Description:
Position Overview :We are seeking a seasoned Design Verification Lead with extensive experience in IP and Subsystem level verification. The ideal candidate will have a deep understanding of PCIe protocols (Gen4/Gen5/Gen6) and AXI protocols, as well as hands-on experience with SystemVerilog UVM (Universal Verification Methodology) for testbench development. The role demands strong debugging skills and the ability to lead verification efforts effectively.Key Responsibilities :PCIe Protocol Verification : - Verify PCIe protocols (Gen4/Gen5/Gen6) ensuring compliance with standards.- Work with PCIe transaction layers, routing, reset flows, and other related functionalities.Subsystem Verification :- Conduct verification of NOC (Network on Chip) subsystems.- Verify AXI protocols within the subsystem context.Testbench Development :- Develop and maintain testbenches using SystemVerilog UVM.- Implement and execute test plans to ensure comprehensive coverage of design specifications.Debugging and Issue Resolution :- Utilize strong debugging skills to identify, diagnose, and resolve verification issues.- Collaborate with design and architecture teams to address and resolve issues effectively.Performance Verification :- (Optional) Contribute to performance verification tasks to ensure system meets performance requirements.Leadership and Collaboration :- Lead the verification team, providing guidance and mentorship to junior verification engineers.- Coordinate with cross-functional teams to align verification activities with project goals.Required Skills :Technical Expertise :- 10-12+ years of experience in IP and Subsystem level verification.- Proficiency in verifying PCIe protocols (Gen4/Gen5/Gen6) with a deep understanding of PCIe transaction layers, routing, and reset flows.- Solid experience with AXI protocols and NOC subsystem verification.Verification Methodologies :- Strong knowledge of SystemVerilog UVM with hands-on experience in testbench development and maintenance.- Proven ability to develop comprehensive test plans and execute them effectively.Debugging :- Excellent debugging skills to troubleshoot and resolve verification issues.- Experience with debugging tools and techniques.Performance Verification :- Knowledge of performance verification methodologies and tools is a plus.Leadership :- Demonstrated ability to lead and mentor a team of verification engineers.- Strong project management skills to ensure verification activities are on track.Soft Skills :- Excellent communication skills to work effectively with cross-functional teams.- Strong analytical and problem-solving abilities. (ref:hirist.tech)
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More About this Listing: Design Verification Lead - System Verilog (10-12 yrs) Anywhere in India/Multiple
Design Verification Lead - System Verilog (10-12 yrs) Anywhere in India/Multiple is a Jobs Design Verification Lead Job at Spruce IT located in India. Find other listings like Design Verification Lead - System Verilog (10-12 yrs) Anywhere in India/Multiple by searching Oodle for Jobs Design Verification Lead Jobs.
Design Verification Lead - System Verilog (10-12 yrs) Anywhere in India/Multiple is a Jobs Design Verification Lead Job at Spruce IT located in India. Find other listings like Design Verification Lead - System Verilog (10-12 yrs) Anywhere in India/Multiple by searching Oodle for Jobs Design Verification Lead Jobs.